1. Field of the Invention
The present invention relates to a semiconductor device with a multilayer interconnection structure and a method of fabricating the same.
2. Description of the Related Art
Recent structural miniaturization in semiconductor devices and scale-down in design rules have found a multilayer interconnection technology essential. Many techniques have been developed for multilayer interconnection. For example, JP-2005-142493A discloses a nonvolatile semiconductor memory device in which first source lines are connected via source line contacts on an element region of a semiconductor substrate. Source shunt lines are connected via first contacts on the first source lines. The source shunt lines are arranged in the same layer as bit line structures. Second source lines are connected via second contacts on the source shunt lines.
A large number of bit lines having respective widths with the value of F in the design rules are arranged in the same layer. On the other hand, each source shunt line structure is composed of a wider wiring having a width larger than the value of F in the design rules in order to reliably receive a source potential Vss from the second source line and to reliably supply the source potential Vss to the first source line.
Dummy spaces each of which has the same width as the wider wiring need to be provided at widthwise ends of the wider wiring in order that a sufficient width of the wider wiring may be ensured. The provision of the dummy spaces results from limitations in a lithography process. Furthermore, in order that a source node potential may be maintained at a predetermined value as much as possible, source shunt lines are provided periodically at every block so that source line potential Vss is stably supplied. However, when the source shunt lines and dummy spaces are periodically arranged for every block, a region where bit lines are to be arranged is reduced such that a reduction in a chip area occurs.
Furthermore, in order that the aforesaid wider wiring and dummy spaces may be formed, a photomask used in exposure to light needs to be provided with a pattern with a width differing from a pattern corresponding to a line width of a bit line. In this case, margins provided for exposure, illumination conditions and an optical proximity correction need to be optimized, whereupon a design efficiency is lowered. Moreover, when images of patterns with different widths are transferred to a resist, a problem of resist pattern collapse or the like occurs, thereby reducing the yield.